1. Field of the Invention
The present invention relates to a testing apparatus and a testing method. More particularly, the present invention relates to a testing apparatus and a testing method for testing a memory under test.
2. Related Art
FIG. 7 is a view showing a configuration of a NAND type flash memory. A memory cell array of the NAND type flash memory has a structure significantly divided into three areas. The first area is a main area used as a data storing area for storing data, the second area is an extended area for storing bad information to distinguish whether the main area is normal or not, and the third area is a special area for storing manufacturing information, ID management information, and bad information such as map information of a bad block. Then, the NAND type flash memory includes a plurality of block areas respectively having a plurality of page areas respectively including a main area and an extended area.
When a partially bad cell exists in a specific block area by adopting the structure divided as described above, since a bad code that is an example of bad information showing that this block area is bad is recorded in an extended area of the block area, it can be controlled so that a user does not use this block area. Moreover, since an error correction code for ECC correction is recorded and used in the extended area of the block area, it can be treated as a non-defective unit. As a result, a manufacturing yield can be improved and a memory unit price can be reduced. However, in order to test and relieve a NAND type flash memory with a bad cell, a complicated test item is required and a testing time becomes increased. Therefore, a development of a testing apparatus for efficiently testing and relieving a NAND type flash memory has been progressed.
FIG. 8 is a view showing a configuration of a testing apparatus 800 according to a conventional art. The testing apparatus 800 includes a pattern generator 802, a main waveform shaper 804, a plurality of individual test units 806, an interface 808, a CPU 810, and a tester bus 812. Each of the plurality of individual test units 806 has a universal buffer memory 822, an internal bus 823, a block fail memory 824, a bad block counter 826, a sub waveform shaper 832, a logic comparator 834, a multiplexer 836, a driver 838, and a level comparator 840, and is provided corresponding to each of a plurality of memories under test (hereinafter, referred to as “DUT”) 850.
The pattern generator 802 generates an address signal and a data signal to be supplied to the plurality of DUTs 850, and supplies the generated signals to the main waveform shaper 804. Moreover, the pattern generator 802 supplies the generated address signal to a plurality of block fail memories 824. Moreover, the pattern generator 802 generates an expectation signal to be output from the DUT 850 according to the address signal and the data signal, and supplies the generated signal to the logic comparator 834. The main waveform shaper 804 shapes the address signal and the data signal generated from the pattern generator 802 into a waveform with a format required for a test of the DUT 850, and supplies the shaped waveform to the DUT 850 via the multiplexer 836 and the driver 838.
The logic comparator 834 compares an output signal from the DUT 850 converted into a binary value by the level comparator 840 and an expectation signal supplied from the pattern generator 802 to generate fail data and supplies the data to the block fail memory 824 when the output signal and the expectation signal are not identical with each other. The block fail memory 824 stores the fail data generated from the logic comparator 834 in association with an address shown by the address signal supplied from the pattern generator 802. The bad block counter 826 counts the fail data generated from the logic comparator 834 to count the number of bad block areas in the DUT 850.
The CPU 810 refers to the block fail memory 824 via the interface 808, reads the fail data stored on the block fail memory 824, and generates bad address information showing block addresses of the bad block areas in the DUT 850 based on the read fail data. Then, the CPU 810 supplies the bad address information to the universal buffer memory 822 via the interface 808.
The universal buffer memory 822 stores the bad address information generated from the CPU 810. Then, the universal buffer memory 822 sequentially supplies the bad address information showing the block addresses to the sub waveform shaper 832. The sub waveform shaper 832 generates an address signal to be supplied to the DUT 850 and supplies the generated signal to the DUT 850 via the multiplexer 836 and the driver 838 based on a block address shown by the bad address information supplied from the universal buffer memory 822, in order to write bad information into an extended area in a block area shown by the bad address information stored on the universal buffer memory 822.
FIG. 9 is a schematic view showing a data transfer process in the testing apparatus 800 according to a conventional art. The CPU 810 performs a data transfer from/to the universal buffer memory 822 and the block fail memory 824 via the interface 808. In addition, since this data transfer is performed via the tester bus 812, it cannot be performed during a test for the DUT 850 and it should be performed at a time after a test termination for the DUT 850. Moreover, the CPU 810 sequentially generates bad address information respectively corresponding to fail data stored on a plurality of universal buffer memories 822 by a serial process. Therefore, when a number of DUTs 850 are simultaneously tested, since an overhead of data transfers is also generated to cause the increase of a transfer time and a waiting time for use in generating bad address information by the CPU 810 is required, a throughput for the test cannot be improved.